In computer networks, internetworking, communications, integrated circuits, etc., where there is a need to communicate information, there are interconnections established to facilitate the transfer of the information. Interconnects may provide the physical communication network between two agents such as agents of Intellectual Property (IP) blocks. When designing systems that comprise such IP blocks and interconnects, testing and simulation occurs prior to the fabrication of a System on a Chip (SoC) containing the IP blocks.
Before the SoC design can be manufactured, it should first be designed, modeled, and verified. SystemC, a modeling language and simulation environment, is an excellent choice for building a software simulation model of the SoC. Just as the physical hardware is designed by choosing IP blocks and then connecting them together with interfaces, the software simulation model is built from behavioral models of the IP blocks that are then connected together by channel models.
A behavioral model may be an encoded formal abstract definition of the hardware/IP block device being modeled. The behavioral model describes the hardware/IP block devices basic components, their properties, available operations, operation granularity, etc. The behavioral model allows designers to analyze intrinsic operation of a single component and/or the entire system while ignoring many implementation issues.
Software simulation models are built to provide high level models of a chip or system design. One form of higher level modeling is transaction level modeling, where data and commands may be sent from one module to another through function calls. Software simulation models may use burst transactions to increase the simulation speed. However, the cycle timing accuracy of this type of models can be much lower comparing to their corresponding physical hardware system. A burst transaction is the sending of a whole group of individual data words over an interconnect in response to a single request. The burst transaction modeling scheme for Open Core Protocol (OCP) communications modeling may be referred to as TL2 for “transaction level 2”. The slower, one data word transmitted per request method of sending a request across an OCP channel is called TL1 for “transaction level 1”. TL1 attempts to capture the cycle timing and ordering of the hardware connection being modeled.
A previous OCP TL2 software simulation model sent bursts through the channel without any explicit timing information for each data word. When a module received a burst transaction of, for example, 10 data words, the receiving module had no timing information to determine when each of the individual data words would have arrived. Thus, generally this previous OCP TL2 simulation model may not be used by an architect who wants the fast simulation turnaround time of such a high level simulation model of the system, but also demands high cycle timing accuracy from the simulation model (for instance, 75% or higher cycle timing accuracy when compared to the corresponding physical hardware).